The development of integrated circuits has made it possible to place many circuit elements in a single semiconductor chip. Where part or all of the circuit is an analog circuit, such as a radio frequency transmitter or receiver, audio amplifier, or other such circuit, circuit design requires lumped elements that cannot be readily realized in monolithic integrated circuits. Capacitors in particular are frequently created as separate elements from the integrated circuit. The electronic device thus typically includes monolithic integrated circuits combined with external capacitors.
For such applications, monolithic ceramic capacitors have been used. For example, single capacitors made of ceramic materials, are known in the art. These are relatively small in size and can be surface mounted to a surface mount circuit board, or glued and wire bonded to a substrate in a hybrid circuit layout.
FIG. 1A shows a lumped element model for a capacitor. In this ideal model, the capacitor provides an ideal voltage/current relationship:
  i  =      C    ⁢                  ⅆ        v                    ⅆ        t            Unfortunately, particularly at high frequencies, capacitors used in electronic circuits deviate substantially from this ideal relationship. These deviations are generally modeled as an equivalent series resistance and equivalent series inductance, along with a capacitance that varies over frequency. In accordance with this model, a capacitor behaves as a series L-R-C circuit as illustrated in FIG. 1B. At lower frequencies, the dominant impedance is the capacitive element C; however, at increasing frequencies the impedance of the capacitive element C decreases and the impedance of the inductive element L increases; until, at the resonant angular frequency (LC)−0.5, the inductive element becomes predominant, and the element ceases performing as a capacitor. Simultaneously, the capacitor dissipates some stored energy (typically through heating of conducting plates and traces), as represented by the series resistance R.
Capacitor design typically must compromise between capacitance value and equivalent series resistance and inductance; greater capacitance typically can be created only at the cost of increased series resistance and inductance. Accordingly, equivalent series resistance and inductance are not avoidable, and electronic design must take them into account, particularly in high frequency products such as broadband receiver/transmitters, short wave devices, and the like.
Various monolithic ceramic structures have been developed to provide relatively small capacitors for highly integrated applications. A first such structure, shown in FIG. 2A, is known as a “multilayer ceramic capacitor”. This structure is formed by stacking sheets of green tape or greenware, i.e., thin layers of a powdered ceramic dielectric material held together by a binder that is typically organic. Such sheets, typically, although not necessarily, of the order of five inches by five inches, can be stacked with additional layers, thirty to one hundred or so layers thick. After each layer is stacked, conductive structures are printed on top of the layer, to form internal plates that form the desired capacitance. When all layers are stacked, they are compressed and diced into capacitors. Then, the compressed individual devices are heated in a kiln according to a desired time-temperature profile, driving off the organic binder and sintering or fusing the powdered ceramic material into a monolithic structure. The device is then dipped in conductive material to form end terminations for the internal conductive structures, suitable for soldering to a surface mount circuit board or gluing and wire bonding to a hybrid circuit.
The printed conductive structures are arranged in a pattern that provides one or more parallel-plate capacitors. For example, in the typical structure shown in FIG. 2A, internal plates 10 and 11 have been formed which extend from alternate sides of the combined structure. The conductive material 12 and 13 at each end forms a common connection point for each plate extending to that side. Plates 10 extend in pairs, each including an upper plate 10 and a lower plate 10′ from the left side, and plates 11 extend similarly in pairs, each including an upper plate 11 and a lower plate 11′ from the right side, forming parallel plate capacitors between each set of adjacent plates 10 and 11′ and 10′ and 11. The illustrated structure is arranged to reduce equivalent series resistance and inductance, by virtue of the plates 10 and 11 extending in pairs from each side. In other embodiments, plates extend individually from opposite sides, such as in the multilayer ceramic capacitor shown in FIGS. 7A and 7B and discussed below.
Each pair of overlapping plates 10 and 11 extending from opposite side metallizations 12 and 13, forms a parallel plate capacitor, such that the entire device forms a network of parallel connected capacitors as shown in FIG. 2B, which can be soldered to the traces 14 of a surface mount circuit board. The resulting equivalent capacitance value is relatively large for the device size, albeit subject to imperfections due to resistance in the many current-carrying conductive structures, and inductance resulting from many plates carrying currents flowing in opposite directions.
FIG. 3A shows an alternative known capacitor structure developed by Dielectric Laboratories, Inc. of Cazenovia, N.Y. and described in detail in U.S. Pat. No. 6,208,501. This structure includes a ceramic chip 20 having conductive end plates on its opposed surfaces, which is bonded by conductive epoxy 22 to conductive end terminations 24 which can then be soldered to the traces 26 on a surface mounting circuit board. As can be seen in FIG. 3B, the net effect is a single capacitor, rather than a parallel array, between the conductive ends of the device. As there is only one capacitor in this device, it has good high frequency performance (reduced resistance and inductance) but has a relatively low capacitance value.
FIG. 4A shows a second alternative capacitor structure developed by American Technical Ceramics Corporation and described in detail in U.S. Pat. No. 5,576,926. This structure includes a layered ceramic chip having an internal conductive plate 30 positioned to overlay conductive plates 32 and 33 extending along an outer surface of the device from conductive end terminations 34 and 35. As before, the conductive end terminations may be readily soldered to the traces 36 of a surface mount circuit board. As seen in FIG. 4B, the net effect is a series combination of two capacitors, between the conductive ends of the device. As in this case there is a series combination of capacitors (which has a lower capacitance value than either capacitor individually), the device has good high frequency performance but relatively low capacitance value.
A third alternative capacitor is shown in FIG. 5A. Here, the ceramic chip 20 with opposed conductive surfaces, shown in FIG. 3A, has been mounted directly to the trace 40 of a hybrid circuit device. The opposed side of the capacitor has been wire bonded through wire bond 42, to the opposite trace 44 of the hybrid device. In this case, the equivalent circuit diagram (FIG. 5B), and performance issues are the same as those with regard to the capacitor of FIG. 3A.
A final alternative capacitor is shown in FIG. 6A. Here, a series capacitor (FIG. 6B) has been formed between metallizations 51, 52 and 53 that are strictly on the outer surfaces of a ceramic chip 50. This alternative is similar to the device shown in FIG. 4A, but the internal metallization has been moved to the outer surface. This device is less complex to manufacture than the device of FIG. 4A, but provides lower capacitance value owing to the distance between the metallization layers 51 and 53 and the opposed metallization layer 52.
As can be seen, each known structure represents a tradeoff between capacitance value and broadband performance. One known approach to managing series resistance and series inductance, is to parallel connect two capacitors, such as shown in FIG. 7. In FIG. 7, a larger value capacitor C1, chosen for its large capacitance value, is connected in parallel to a smaller value capacitor, chosen for its small equivalent series resistance. As will be appreciated, this circuit exhibits multiple resonant frequencies, a first at the frequency (L1C1)−0.5, and a second at the frequency (L2C2)−0.5. Typically the larger valued capacitor C1 would have the larger series resistance and inductance value and thus the lower resonant frequency, whereas the smaller valued capacitor C2 would be chosen for high frequency performance resulting from low series resistance and series inductance values. At low frequencies, the larger value of C1 will produce acceptable performance, whereas at higher frequencies, where C1 behaves increasingly less like a capacitor and more like an inductance, C2 will be below its resonant frequency and perform well as a capacitor throughout the frequency of interest.
The parallel capacitor approach has been utilized in conjunction with ceramic chip capacitors, to improve the high frequency performance of those capacitors. Specifically, referring to FIG. 8A, one known broadband ceramic capacitor structure uses a multilayer capacitor, such as that described above with reference to FIG. 2A, which is stacked above and soldered or bonded to a single layer, high frequency capacitor such as that described above with reference to FIG. 3A. The resulting combined structure is wave soldered or bonded together with epoxy, producing a parallel combination of low and high-frequency capacitors seeking to achieve broadband performance. A second known implementation of this concept is shown in FIG. 8B. There, one of the side terminals of a multilayer capacitor such as described above with reference to FIG. 2A, is tilted against the upper surface of a single-layer, high frequency capacitor such as that described above with reference to FIG. 6A. The upper surface of the single-layer capacitor thus forms a first terminal of a parallel capacitor combination, that is wire bonded to a circuit board trace 36 in the manner described above with reference to FIG. 5A. The opposite side terminal of the multi-layer capacitor and the bottom surface of the single-layer capacitor are connected to a second trace 36 of the circuit board, thus forming the second terminal of the combined parallel capacitor combination.
While parallel capacitor combinations such as shown in FIGS. 8A and 8B have been used with some success in commercial devices, these combinations suffer from a number of drawbacks. First, the measured capacitance of these parallel combinations exhibit variations (resonances and dropouts), likely due to a mismatch between the resonances of the effective L-R-C circuits that are created by the parallel connected capacitors. Furthermore, the upper frequency response of even these parallel combinations may not meet the requirements of very wide band (GHz) devices in current use. Also, the mechanical stacking of dual ceramic capacitors in the manner shown is not easily compatible with “tape and reel” assembly methods and thus, are cumbersome and expensive to implement in mass production. Further, mechanically stacking dual ceramic capacitors increases the overall height of the circuit board assembly above that of a board having only single ceramic capacitors.
There accordingly is a remaining need for a broadband capacitor meeting the performance needs of modern wideband circuits, while maintaining the size and cost efficiencies of existing ceramic capacitors.